The present invention relates to integrated circuit memory devices, and more particularly, to multi-block memory devices.
FIG. 1 shows a semiconductor memory device having conventional row decoders. With reference to FIG. 1, conventional row decoders used in devices, such as flash memory devices may include word line decoders (for example, 111) and source line decoders (for example, 115), employed in each of a plurality of memory blocks 110, 120, . . . , 130. Memory blocks 110, 120, . . . , 130 each have cell arrays (for example, 113) in addition to the decoders. Cell arrays 113, 123, . . . , 133 include cell transistors that store cell data, as shown, for example, in FIG. 5.
FIG. 2 is a simplified circuit diagram of one of word line decoders 111, 121, . . . , 131 shown in FIG. 1. Logic gates 210-230 decode sub-block selection signals P, Q, R, S, Mi and output a word line signal DWLi on a word line in a cell array 113, 123, . . . , 133. If the cell arrays 113, 123, . . . , 133 each include 2048 (2k) word lines, according to the above, P includes 4 signals to select one of 4 highest-order sub-blocks in the memory blocks 110, 120, . . . , 130 corresponding to Mi, Q includes 8 signals to select one of 8 sub-blocks in the sub-blocks selected by P, R includes 8 signals to select one of 8 sub-blocks in the sub-blocks selected by Q, and S includes 8 signals to select one of 8 sub-blocks in the sub-blocks selected by R.
FIG. 3 is a simplified circuit diagram of one of source line decoders 115, 125, . . . , 135 shown in FIG. 1. Logic gates 310–330 decode the sub-block selection signals P, Q, R, S, Mi, and output a source line signal DSLi on a source line in a respective cell array 113, 123, . . . , 133. Also, as shown in FIG. 2, if cell arrays 113, 123, . . . , 133 are each composed of 2048 (2k) word lines, T includes 4 signals to select a source line corresponding to predetermined segments selected by S. The number of T signals is half of the number of S signals, as each T signal controls two cell transistors connected to two respective word lines as shown in FIG. 5.
The sub-block selection signals P, Q, R, S, T, Mi are produced by a decoder that decodes an externally supplied address signal. In a conventional row decoder of a flash memory device, in order to operate many memory blocks 110, 120, . . . , 130 composed of 2048 (2k) word lines as shown in FIG. 1, 54 signal lines are used to transmit the sub-block selection signals P, Q, R, S, T and Mi for each of the memory blocks 110, 120, . . . , 130.
In a conventional device as described above, the larger the memory, the greater the number of memory blocks 110, 120, . . . , 130, and accordingly, the greater the number of word line decoders 111, 121, . . . , 131 and source line decoders 115, 125, . . . , 135. If there are a large number word line decoders 111, 121, . . . , 131 and source line decoders 115, 125, . . . , 135, an even larger number of signal lines may be used to transmit the sub-block selection signals P, Q, R, S, T, Mi, which can consume a significant amount of chip real estate.